While the development scale of LSIs (large scale integrated circuits) has been increased in recent years, the development period thereof has been reduced. Also, reductions in power consumption of LSIs have been a major challenge. Accordingly, in designing an LSI, the performance and power consumption of the LSI must be estimated in the initial stage. In order to estimate the performance and power consumption of the entire LSI, the components of the LSI, circuit modules, are converted into performance models (hereafter referred to as “models”).
Examples of the technology for modeling circuit modules include a technology that converts a low-level circuit description [e.g., hardware description language (HDL)] into a high-level circuit description [e.g., transaction-level model (TLM)]. This technology performs a simulation in a low-level circuit description and extracts a transaction from the result of the simulation. During this process, a signal pattern is mapped into a message, which is then converted into the transaction. Subsequently, a model is extracted. In extracting the model, attention is paid to the repeating mutual relationship between the input sequence and the output sequence, and a neural network is used to generate output messages and to estimate the statistic behavior of components. Data dependency is also extracted. Finally, a highly abstracted model is generated. This model is obtained by analyzing an input transaction or message and then outputting an output transaction or message. During that process, attention is paid not to the signal level or the like but to the timing of the message or the relationship. However, how the simulation is performed is not examined in detail.
In order to logically verify a digital system including an LSI, an external module communicating with the hardware to be verified is simulated using software. Used at that time is a technology for delaying the frequency at which the clock is provided to the hardware. This technology, however, has nothing to do with model generation.
There is also a technology that, in performing a simulation of cycle-accurate operation or a simulation of function and logic, explores various designs with respect to clock frequency control on each of the function blocks of an LSI design or buffer insertion while easily changing the configuration. Specifically, the technology includes frequency control means that, in verifying function and logic using data of an LSI design as an input, assigns the operating frequency to each of the function blocks constituting the LSI to be verified, clock frequency change means that changes the operating clock of each function block in accordance with the operating frequencies assigned by the frequency control means, and function simulation means that performs a function simulation of the operating clock-changed LSI. The frequency control means assigns all the function blocks the operating frequencies corresponding to the states thereof. The clock frequency change means changes the operating clock of each function block in accordance with the assigned operating frequencies. The function simulation means performs a function simulation of the LSI including the operating clock-changed function blocks. The above-mentioned process is repeated to obtain an optimum solution. As seen, an operating clock suitable for each function block is easily assigned and then the LSI is verified by performing a function simulation of the entire LSI. For this reason, this technology is believed to be capable of efficiently verifying the designs of LSIs with a short turnaround time as a whole. In this technology, however, it is not considered to generate a model.
In order to generate models accurately as described above, modules having complicated functions must be simulated under various operating conditions. However, preparing an enormous amount of simulation input data usually necessary to realize “various operating conditions” requires sufficient understanding of the function specification of each module, requiring much time and effort. That is, models are not easy to generate.